T R A C K       P A P E R
ISSN:2394-3661 | Crossref DOI | SJIF: 5.138 | PIF: 3.854

International Journal of Engineering and Applied Sciences

(An ISO 9001:2008 Certified Online and Print Journal)

High Speed AES Cipher Engine

( Volume 2 Issue 7,July 2015 ) OPEN ACCESS
Author(s):

Ms.Anuradha Balasubramaniam

Abstract:

For secure data transmission cryptographic algorithms are used for many applications. This paper introduces optimized hardware implementation of area and speed improvement for the block cipher Advanced Encryption Standard (AES-128) using Field Programmable Graphic Array (FPGA). As AES has four transformations among them sub-byte and mix-column transformation are key challenges to implement in terms of area and speed. In this research proposes new method of mix-column transformation which uses logical shift and Xor operation. This hardware implementation achieves  the maximum clock frequency of 188.893 MHz is, in feedback encryption modes and uses less number of slices 427.

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